Data storage device and operating method thereof

ABSTRACT

A data storage device may include a nonvolatile memory apparatus and a controller. The controller may be configured to translate a logical address into a physical address when receiving a host command (such as a write command or a read command) including the logical address from a host device, to generate a pre-command including the physical address, to transmit the generated pre-command to the nonvolatile memory apparatus before completing one or more remaining operations of the operations used to process the host command, and to transmit a confirm command to the nonvolatile memory apparatus when the remaining operations are complete. The controller may perform the remaining operations and the transmission of the pre-command to the nonvolatile memory apparatus at the same time.

CROSS-REFERENCES TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) toKorean application number 10-2019-0148385, filed on Nov. 19, 2019, inthe Korean Intellectual Property Office, which is incorporated herein byreference in its entirety.

BACKGROUND 1. Technical Field

Various embodiments generally relate to a data storage device and anoperating method thereof.

2. Related Art

Since a data storage device using a memory device has no mechanicaldriver, the data storage device has excellent stability and durability,very high information access speed, and low power consumption. Datastorage devices having such advantages includes a universal serial bus(USB) memory device, a memory card having various interfaces, auniversal flash storage (UFS) device, and a solid state drive (SSD).

In a flash storage device using NAND flash memory, an FTL (FlashTranslation Layer) may translate an LPN (Logical Page Number) receivedfrom a host into a PPN (Physical Page Number), packetize the PPN withother parameters, and transfer the packetized PPN to a NAND flashcontroller. Then, the NAND flash controller may perform a scheduling andparsing operation, and then transfer the parsed PPN in the form of anaddress to the NAND flash memory.

With the gradual improvement in NAND flash I/O speed, the detrimentaleffect of the time required to provide the NAND command to the NANDflash memory (i.e., the NAND command transmission time) on theperformance of flash storage devices is increasing.

SUMMARY

Various embodiments are directed to a data storage device capable ofimproving data write and read performance by shortening a NAND commandtransmission time, and an operating method thereof.

In an embodiment, a data storage device may include: a nonvolatilememory apparatus; and a controller configured to: receive a host commandincluding a logical address, determine a physical address correspondingto the logical address, generate a pre-command including the physicaladdress, transmit the generated pre-command to the nonvolatile memoryapparatus before completing performance of one or more remainingoperations used to process the host command, and transmit a confirmcommand to the nonvolatile memory apparatus when performance of theremaining operations is complete, wherein the controller performs theremaining operations and the transmission of the generated pre-commandto the nonvolatile memory apparatus at the same time.

In an embodiment, an operating method of a data storage device mayinclude the steps of: receiving a host command including a logicaladdress; determining a physical address corresponding to the logicaladdress; generating, according to a specification of the host command, apre-command which includes the physical address; transmitting thepre-command to the nonvolatile memory apparatus before completing one ormore remaining operations used to process the host command; performingthe remaining operations; and transmitting a confirm command to thenonvolatile memory apparatus when performing the remaining operations iscomplete, wherein performance of the remaining operations andtransmission of the pre-command to the nonvolatile memory apparatusoccur at a same time.

In accordance with the present embodiments, while an FTL operation isperformed, a NAND command including some parameters can be transmittedfrom the point of time that a PPN is decided. Thus, a part of the FTLoperation and the NAND command transmission can be performance at thesame time. Therefore, the NAND command transmission time can besubstantially reduced, which makes it possible to expect that data writeor read performance will be able to be improved.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a configuration of a data storage device inaccordance with an embodiment.

FIG. 2 illustrates a command transmission procedure in accordance withthe present embodiment.

FIGS. 3, 4, and 5 each illustrate a pre-command transmission procedurein accordance with an embodiment.

FIGS. 6 and 7 each illustrate a command transmission procedure inaccordance with the embodiment.

FIG. 8 is a flowchart describing an operating process of a data storagedevice in accordance with an embodiment.

FIG. 9 illustrates a data processing system including an SSD (SolidState Drive) in accordance with an embodiment.

FIG. 10 illustrates a configuration of a controller of FIG. 9.

FIG. 11 illustrates a data processing system including a data storagedevice in accordance with an embodiment.

FIG. 12 illustrates a data processing system including a data storagedevice in accordance with an embodiment.

FIG. 13 illustrates a network system including a data storage device inaccordance with an embodiment.

FIG. 14 illustrates a nonvolatile memory apparatus included in a datastorage device in accordance with an embodiment.

DETAILED DESCRIPTION

Hereinafter, a data storage device and an operating method thereofaccording to the present disclosure will be described below withreference to the accompanying drawings through exemplary embodiments.

FIG. 1 is a diagram illustrating a configuration of a data storagedevice 10 in accordance with an embodiment.

Hereafter, the data storage device 10 will be described with referenceto FIG. 2 which is a diagram for describing a command transmissionprocedure in accordance with the present embodiment, FIGS. 3 to 5 whichare diagrams for describing a pre-command transmission procedure inaccordance with an embodiment, and FIGS. 6 and 7 which are diagrams fordescribing the command transmission procedure in accordance with theembodiment in more detail.

The data storage device 10 may store data accessed by a host device (notillustrated) such as a mobile phone, MP3 player, laptop computer,desktop computer, game machine, TV or in-vehicle infotainment system.The data storage device 10 may be referred to as a memory system.

The data storage device 10 may be fabricated as any one of variousstorage devices, according to an interface protocol coupling the datastorage device 10 to the host device. For example, the data storagedevice 10 may be configured as any one of various types of storagedevices which include an SSD (Solid State Drive), an MMC (Multi-MediaCard) such as an eMMC, RS-MMC or micro-MMC, an SD (Secure Digital) cardsuch as a mini-SD or micro-SD, a USB (Universal Serial Bus) storagedevice, a UFS (Universal Flash Storage) device, a PCMCIA (PersonalComputer Memory Card International Association) card-type storagedevice, a PCI (Peripheral Component Interconnection) card-type storagedevice, a PCI-E (PCI Express) card-type storage device, a CF (CompactFlash) card, a smart media card and a memory stick.

The data storage device 10 may be fabricated as any one of various typesof packages. For example, the data storage device 10 may be fabricatedas any one of various types of packages such as a POP(Package-On-Package), SIP (System-In-Package), SOC (System-On-Chip), MCP(Multi-Chip Package), COB (Chip-On-Board), WFP (Wafer-level FabricatedPackage) and WSP (Wafer-level Stack Package).

The data storage device 10 may include a nonvolatile memory apparatus100 and a controller 200.

The nonvolatile memory apparatus 100 may write or read data to or froman address corresponding to a flash write command or flash read commandtransmitted from the controller 200. In the present embodiment, each ofthe flash write command and the flash read command may include apre-command and a confirm command. The pre-command may include commandparameters which can be transmitted before the corresponding confirmcommand is transmitted, and the confirm command may control thenonvolatile memory apparatus 100 to actually start a write or readoperation. The command parameters which can be transmitted before theconfirm command may be configured according to an operator's needs, andwill be described below in detail.

The nonvolatile memory apparatus 100 may operate as a storage medium ofthe data storage device 10. The nonvolatile memory apparatus 100 may beconfigured as any one of various types of nonvolatile memory apparatusessuch as a NAND flash memory, NOR flash memory, FRAM (FerroelectricRandom Access Memory) using a ferroelectric capacitor, MRAM (MagneticRandom Access Memory) using a TMR (Tunneling Magneto-Resistive) layer,PRAM (Phase Change Random Access Memory) using chalcogenide alloys, andReRAM (Resistive Random Access Memory) using transition metal oxide,depending on memory cells.

The nonvolatile memory apparatus 100 may include a memory cell array(not illustrated) having a plurality of memory cells arranged atrespective intersections between a plurality of bit lines and aplurality of word lines (as shown in FIG. 14). Each of the memory cellsof the memory cell array may be a single level cell (SLC) for storing1-bit data, a multi-level cell (MLC) for storing 2-bit data, a triplelevel cell (TLC) for storing 3-bit data, or a quadruple level cell (QLC)for storing 4-bit data. The memory cell array may include one or more ofthe SLCs, the MLCs, the TLCs and the QLCs. The memory cell array mayinclude memory cells configured in a two-dimensional horizontalstructure or memory cells configured in a three-dimensional verticalstructure.

The controller 200 may process a read command or write command receivedfrom the host (that is, a host command) by performing a plurality ofoperations. When receiving the host command that includes an LPN(Logical Page Number) from the host device, one of the operationsperformed by the controller 200 may be translation of the LPN into a PPN(Physical Page Number), with a first set of operations for processingthe command being performed before or in parallel with the translationoperation, and a second set of operations for processing the commandbeing performed after the translation operation but before thenonvolatile memory apparatus 100 starts the corresponding read or writeoperation. In an embodiment, after the translation operation determinesthe PPN, the controller 200 may generate a pre-command including thePPN, and transmit the generated pre-command to the nonvolatile memoryapparatus 100. The pre-command may be transmitted before completion ofthe second set of operations. In an embodiment, processing the hostcommand may include the performance of a third set of operations inresponse to the nonvolatile memory apparatus 100 completing thecorresponding read or write operation.

When the controller 200 finishes performing the remaining operationsother than the operations already performed to generate the pre-command(that is, when the controller 200 has completed the second set ofoperations), the controller 200 may transmit a confirm command to thenonvolatile memory apparatus 100. The pre-command may be a commandgenerated according to the information specified by the read or writecommand, based on a pre-command packet including command parameterswhich can be transmitted to the nonvolatile memory apparatus 100 beforethe confirm command at or after a point of time that a physical addressfor a logical address transmitted from the host device has beendetermined. In an embodiment, the controller 200 may determine that thepoint of time that a command parameter which can be transmitted beforethe confirm command to the nonvolatile memory apparatus 100 is prepared(for example, the point of time at which a physical addresscorresponding to the logical address of the host command is determined)is the point of time to transmit the pre-command to the nonvolatilememory apparatus 100.

Referring to FIG. 3, when the host command is a read command, thecontroller 200 may generate a pre-command packet including a datastorage method, a flash read command indication, and addressinformation.

A read operation of the nonvolatile memory apparatus 100 may includeboth of an array read operation and a data-out operation, and thepre-command packet may be generated even when only a parameter for thearray read operation has been determined. Thus, the controller 200 maytransmit the pre-command packet to the nonvolatile memory apparatus 100using only the parameter for the array read operation, and then performthe remaining operations for generating a parameter for the data-outoperation. That is, the remaining operations (i.e., the second set ofoperations) during the read operation may include an operation ofgenerating a parameter for the data-out operation including (forexample) buffer allocation. At this time, the remaining operations mayalso include operations for updating meta information such as a readcount.

In general, when the host command is a sequential read commandindicating a 128k read, the controller 200 needs to generate 32 unitparameter sets by dividing the read command by 4 k (corresponding to asize of a logical address unit), and set the data-out operation as wellas the array read operation for the generated 32 unit parameters. Inparticular, since the data-out operation requires a read bufferallocation operation, the controller 200 needs to perform the settingoperation while repeating the read buffer allocation operation 32 times.That is, a NAND command for a general read operation can be transmittedto the nonvolatile memory apparatus 100, after the parameters for thearray read operation and the data-out operation are all generated. Inthe present embodiment, the controller 200 may transmit only theparameter for the array read operation as the pre-command to thenonvolatile memory apparatus 100 in advance of the transmission of theconfirm command. For example, when the host command is a sequential readcommand indicating 128 k read, the controller 200 may transmit thepre-command to the nonvolatile memory apparatus 100 in advance of thetransmission of the confirm command by using only the parameters for thetwo array read operations that read each of four 16 k planes twice toperform the 128 k read. In the above-described example, the sequentialread has been exemplified. However, the present embodiment may also beapplied to random read.

In an embodiment illustrated in FIG. 4, when the host command is a writecommand, the controller 200 may generate a pre-command packet includinga data storage method, a flash write command indication, addressinformation of the nonvolatile memory apparatus, and data to be written.

In another embodiment illustrated in FIG. 5, when the host command is awrite command, the controller 200 may generate a pre-command packetincluding a data storage method, a flash write command indication, andaddress information of the nonvolatile memory apparatus. That is, thepre-command packet for the write command may or may not include userdata Datainput to be written, depending on the embodiment.

In the case of the write operation, the remaining operations may includea Logical-to-Physical (L2P) map table update, a journaling data update,and original write data processing. The journaling data update mayinclude an operation that supports data recovery when a situation suchas a sudden shut-down occurs.

The original write data processing may include an operation ofprocessing original user data to be written for the sake of protectionand security of the original user data.

For example, an original write data processing operation may indicate anoperation of scrambling original user data and writing the scrambleddata to a new region (i.e. a new region of a buffer) within a memory230. The scrambling may indicate an operation of processing the originaluser data through a series of algorithms, according to thecharacteristics of the nonvolatile memory apparatus (for example, NANDflash) 100. For another example, the scrambling may indicate anoperation of encoding the original user data and writing the encodeddata to a new region (i.e. a new region of the buffer) within the memory230. As described above, when the user data is written to thenonvolatile memory apparatus 100, the user data may be not the originaldata, but the processed data.

When data to be written is included in the pre-command packet, theremaining operations do not include the operation of processing originaluser data to be written, since that data has already been sent to thenonvolatile memory apparatus 100 at the time when the remainingoperations are performed.

As shown in FIG. 2, after receiving the host request (i.e., a hostcommand) including a read or write command (at S1), performing alogical-to-physical (L2P) translation (at S2), and sending thepre-command packet to the second core (at S3), the controller 200 mayperform an operation of transmitting the pre-command to the nonvolatilememory apparatus 100 (at S4B) and the remaining operations (such as theFTL process at S4A) which are not involved in generating the pre-commandat the same time. In the present embodiment, the controller 200 canprocess an operation of an FTL core (first core 220 to be describedbelow) and an operation of a NAND core (second core 240 to be describedbelow) in parallel to each other at the same time. After the remainingoperations are completed, the first core may send the post-commandpacket to the second core (at S5), and in response the second core maysend the confirm command to the nonvolatile memory apparatus 100 (atS6). Thus, it is possible to expect that the processing speed of theread/write operation may be improved.

The controller 200 may control overall operations of the data storagedevice 10 by driving firmware or software loaded in the memory 230. Thecontroller 200 may decode and execute a code-based instruction oralgorithm such as firmware or software. The controller 200 may beimplemented in hardware or a combination of hardware and software.

Referring back to FIG. 1, the controller 200 may include a hostinterface 210, a first core 220, the memory 230, and a second core 240.Although not illustrated in FIG. 1, the controller 200 may furtherinclude an ECC (Error Correction Code) engine which generates paritydata by performing ECC encoding on write data provided from a hostdevice and performs ECC decoding on data read from the nonvolatilememory apparatus 100 using the parity data. The ECC engine may beinstalled inside or outside the second core 240.

The host interface 210 may interface the host device and the datastorage device 10 in accordance with a protocol of the host device. Forexample, the host interface 210 may communicate with the host devicethrough any one protocol of USB (Universal Serial Bus), UFS (UniversalFlash Storage), MMC (Multimedia Card), PATA (Parallel AdvancedTechnology Attachment), SATA (Serial Advanced Technology Attachment),SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), PCI(Peripheral Component Interconnection) and PCI-e (PCI express).

Referring to FIG. 6, when a read command including a logical address(i.e., an LPN) is received from the host device, the first core 220 maytranslate the LPN into a PPN, and transfer a pre-command packetincluding the PPN to the second core 240.

Specifically, when a read command including a logical address (such asan LPN) is received from the host device, the first core 220 maytranslate the logical address into a physical address (such as a PPN)corresponding to the logical address by referring to an L2P map tablepreviously stored in the controller 200.

When a write command including a logical address is received from thehost device, the first core 220 may determine a physical address (suchas a PPN) to which data corresponding to the logical address transmittedfrom the host device is to be written. Determining the physical addressmay include associating an unused area of memory corresponding to thephysical address to the logical address.

The above-described pre-command packet may include command informationwhich can be transmitted to the nonvolatile memory apparatus 100, beforethe transmission of a confirm command, immediately after the physicaladdress for the logical address transmitted from the host device hasbeen determined (such as the time indicated by “L2P Translation FinishedHere” in FIG. 6).

For example, the pre-command packet may include a data storage method(e.g., reliability mode, such as SLC, TLC or MLC), a flash write/readcommand indication, and address information. Accordingly, when a readcommand is received from the host device, the pre-command packet mayinclude the data storage method (e.g., the reliability mode), a channel,a chip enable CE, a NAND row address, a NAND column address, and theflash read command indication. For example, in the case of SLC 1-PlaneRead Operation, the pre-command may be configured in a format such asDAh-00h-CCRRR. Here, DAh may represent the data storage method, 00h mayrepresent the flash read command indication, and CCRRR may represent theaddress information, where CC is a column address portion and RRR is arow address portion. As another example, in the case of 4-Plane ReadOperation, the pre-command may be configured in a format such as 00hCCRRR 31h-00h CCRRR 31h-00h CCRRR 31h-00h CCRRR. Here, 00h may representthe flash read command indication, CCRRR may represent the addressinformation, and 31h may represent a plane change command.

When a write command is received from the host device, a pre-commandpacket may include a data storage method (e.g., a reliability mode, suchas SLC, TLC or MLC), a channel, a chip enable CE, a NAND row address, aNAND column address, a buffer address, a flash write command indicationand data to be written. The data to be written may indicate user data.For example, in the case of SLC 1-Plane Write Operation with Datain, thepre-command may be configured in a format such asDAh-80h-CCRRR-DataInput. Here, DAh may represent a data storage method,80h may represent the flash write command indication, CCRRR mayrepresent the address information, and DataInput may represent the datato be written.

In another example, in the case of 4-Plane Write Operation with Datain,the pre-command may be configured in a format such as 80h CCRRR DataIn111h-80h CCRRR DataIn2 11h-80h CCRRR DataIn3 11h-80h CCRRR DataIn4. Here,80h may represent the flash write command indication, CCRRR mayrepresent the address information, DataIn1 to DataIn4 may represent theportions of the data DataIn to be written into the first to fourthplanes, respectively, and 11h may represent a plane change command.

On the other hand, when a write command is received from the hostdevice, a pre-command packet may include the data storage method(reliable mode) such as SLC, TLC or MLC, a channel, a chip enable CE, aNAND row address, a NAND column address, a buffer address, and the flashwrite command indication. That is, the data to be written may not beincluded in the pre-command. The present embodiment is not limitedthereto, but the parameters included in the pre-command packet can bechanged depending on an operator's necessity. In the case of SLC 1-PlaneWrite Operation without Datain, the pre-command may be configured in aformat such as DAh-80h-CCRRR. Here, DAh may represent the data storagemethod, 80h may represent the flash write command indication, and CCRRRmay represent the address information.

The first core 220 may transfer the pre-command packet to the secondcore 240, and perform the remaining operations which do not includethose operation used to generate the pre-command packet (operation S60of FIG. 6). That is, the first core 220 may perform the remainingoperations such as packetizing, which is related to the read/writecommand.

When finished with the remaining operations, the first core 220 maytransmit a post-command packet of FIG. 6 to the second core 240indicating that the second core 240 is to transmit a confirm command.The nonvolatile memory apparatus 100 may start to perform the flash reador write command after receiving the confirm command from the secondcore 240.

In an embodiment, when the first core 220 receives a host abort commandfrom the host device before transmitting the post-command packet to thesecond core 240, the first core 220 may abort the procedure oftransmitting the post-command packet to the second core 240. In otherwords, in response to receiving the host abort command, the first core220 may direct to the second core 240 to not transmit the confirmcommand. As a result, the nonvolatile memory apparatus 100 may notperform the operation corresponding to the pre-command which it hadreceived.

In another embodiment, when the first core 220 receives the host abortcommand from the host device before transmitting the post-command packetto the second core 240, the first core 220 may transmit a post-commandpacket including an abort request to the second core 240. In response toreceiving the post-command packet including the abort request, thesecond core 240 may abort transmitting the pre-command to thenonvolatile memory apparatus 100. When the second core 240 receives thepost-command packet including the abort request after completelytransmitting the pre-command to the nonvolatile memory apparatus 100,the second core 240 may not perform a separate operation on thenonvolatile memory apparatus 100.

The above-described first core 220 may process the request transmittedfrom the host device. In order to process the request transmitted fromthe host device, the first core 220 may execute a code-based instructionor algorithm, i.e. firmware, which is loaded into the memory 230, andcontrol the operations of the nonvolatile memory apparatus 100 andinternal devices such as the host interface 210, the memory 230 and thesecond core 240.

The first core 220 may generate control signals for controlling anoperation of the nonvolatile memory apparatus 100, based on requeststransmitted from the host device, and provide the generated controlsignals to the nonvolatile memory apparatus 100 through the second core240.

The memory 230 may store the L2P map table including a logical addressand a physical address corresponding to the logical address.

The above-described memory 230 may include a dynamic RAM (DRAM) orstatic RAM (SRAM). The memory 230 may store the firmware performed bythe first core 220. Furthermore, the memory 230 may store data requiredfor performing the firmware, for example, metadata. That is, the memory230 may operate as a working memory of the first core 220. Although notillustrated in FIG. 1, the controller 200 may further include a firstcore-dedicated memory disposed adjacent to the first core 220, and thefirmware and meta data stored in the memory 230 may be loaded to thefirst core-dedicated memory.

The memory 230 may include a data buffer for temporarily storing writedata which will be transmitted from the host device to the nonvolatilememory apparatus 100, read data which are read from the nonvolatilememory apparatus 100 and will be transmitted to the host device, orboth. That is, the memory 230 may operate as a buffer memory.

FIG. 1 illustrates that the memory 230 is included in the controller200, but the memory 230 may be outside the controller 200.

The second core 240 may transmit a pre-command, which is generatedaccording to the specification of a write or read command based on apre-command packet, to the nonvolatile memory apparatus 100. Then, afterthe remaining operations are finished, the second core 240 may generatea confirm command based on a post-command packet transferred from thefirst core 220, and transmit the confirm command to the nonvolatilememory apparatus 100.

The second core 240 may store information on a ready status or busystatus of the nonvolatile memory apparatus 100, and transmit apre-command or confirm command when the nonvolatile memory apparatus 100is in the ready status. When the nonvolatile memory apparatus 100 is inthe busy status, the second core 240 may wait without transmitting thepre-command or the confirm command to the nonvolatile memory apparatus100.

The second core 240 may manage transmission statuses includingtransmission start, transmission finish, and transmission preparationfor the pre-command which is to be transmitted to the nonvolatile memoryapparatus 100.

The second core 240 may manage the transmission statuses for thepre-command as follows. When the second core 240 starts to transmit thepre-command to the nonvolatile memory apparatus 100, the transmissionstatus may be set to the transmission start. When the second core 240finishes transmitting the pre-command to the nonvolatile memoryapparatus 100, the transmission status may be set to the transmissionfinish. Before the second core 240 transmits the pre-command to thenonvolatile memory apparatus 100, the transmission status may be set tothe transmission preparation.

Before transmitting the confirm command to the nonvolatile memoryapparatus 100, the second core 240 may check whether the pre-command hasbeen transmitted, based on the transmission status. Then, whentransmitting the confirm command, the second core 240 may determinewhether to transmit the pre-command, that is, whether the pre-commandcorresponding to the confirm command has not been transmitted yet. Whenthe transmission status of the pre-command is the transmissionpreparation, the second core 240 may transmit the confirm command withthe pre-command.

Referring to FIG. 7, when receiving a post-command packet from the firstcore 220 while transmitting the pre-command to the nonvolatile memoryapparatus 100, the second core 240 may transmit the confirm command(indicated in FIGS. 6 and 7 by “Confirm Command Issue”) to thenonvolatile memory apparatus 100 after waiting for the transmission ofthe pre-command (indicated in FIGS. 6 and 7 by “Pre-Command Issue”) tobe completed.

Accordingly, as shown in FIG. 7, at the time the second core 240receives the post-command packet, the second core 240 may check thetransmission status of the pre-command, and determine whether thepre-command is being transmitted to the nonvolatile memory apparatus100.

The second core 240 may control the nonvolatile memory apparatus 100under control of the first core 220. When the nonvolatile memoryapparatus 100 is configured as a NAND flash memory, the second core 240may be referred to as an FCT (Flash Control Top). The second core 240may transmit control signals, generated by the first core 220, to thenonvolatile memory apparatus 100. The control signals may include acommand, an address and an operation control signal for controlling anoperation of the nonvolatile memory apparatus 100. Examples of theoperation control signal may include a chip enable signal, a commandlatch enable signal, an address latch enable signal, a write enablesignal, a read enable signal, a data strobe signal, and the like, butare not limited thereto. The second core 240 may transmit write data tothe nonvolatile memory apparatus 100, and may receive read data from thenonvolatile memory apparatus 100.

The second core 240 and the nonvolatile memory apparatus 100 may becoupled through a plurality of channels CH1 to CHn. The second core 240may transmit signals, such as a command, an address, an operationcontrol signal and data (i.e. write data), to the nonvolatile memoryapparatus 100 through the plurality of channels CH1 to CHn. The secondcore 240 may receive a status signal (for example, ready/busy) and data(i.e. read data) from the nonvolatile memory apparatus 100 through theplurality of channels CH1 to CHn.

FIG. 8 is a flowchart illustrating an operating process of a datastorage device in accordance with an embodiment.

In step S101, the controller 200 may receive a host command (which maybe a write command or a read command) including a logical address fromthe host device.

In step S103, the controller 200 may translate the logical address intoa physical address corresponding to the logical address.

Specifically, when receiving a read command including a logical addressfrom the host device in step S101, the controller 200 may translate thelogical address, included in the read command received from the hostdevice, into a physical address corresponding to the logical address byreferring to a previously-stored L2P map table.

When receiving a write command including a logical address from the hostdevice in step S101, the controller 200 may determine a physical addressto which data corresponding to the logical address received from thehost device is to be written.

In step S105, the controller 200 may generate a pre-command packet whichincludes the physical address and can be transmitted to the nonvolatilememory apparatus 100 before the remaining operations involved inprocessing the command received from the host (i.e., the operations notperformed when producing the pre-command packet) are completed.

Referring to FIG. 3, when receiving a read command from the host device,the controller 200 may generate a pre-command packet including a datastorage method, a flash read command indication, and addressinformation.

Referring to FIG. 4, in an embodiment, when receiving a write commandfrom the host device, the controller 200 may generate a pre-commandpacket including a data storage method, the flash write commandindication, address information, and data to be written.

Referring to FIG. 5, in another embodiment, when receiving a writecommand from the host device, the controller 200 may generate apre-command packet including a data storage method, a flash writecommand indication, and address information.

In step S107, the controller 200 may transmit the pre-command, which wasgenerated according to the specification of the write or read commandbased on the pre-command packet, to the nonvolatile memory apparatus100.

In step S107, the controller 200 may also perform the remainingoperations (operations needed to process the command from the host butnot used to generate the pre-command).

The operation of transmitting the pre-command to the nonvolatile memoryapparatus 100 and performing the remaining operations in step S107 maybe performed at the same time.

In step S109, the controller determines whether the remaining operationsare completed, and waits at S109 until they are. Then, when it isdetermined that the remaining operations are completed, at S111 thecontroller 200 may transmit a confirm command to the nonvolatile memoryapparatus 100.

In steps S107 and S111, when the nonvolatile memory apparatus 100 is inthe ready state, the controller 200 may transmit the pre-command (forstep S107) or the confirm command (for step S111) to the nonvolatilememory apparatus 100.

Although not illustrated, the controller 200 may manage transmissionstatuses including transmission start, transmission finish, andtransmission preparation for the pre-command which is to be transmittedto the nonvolatile memory apparatus 100.

Before transmitting the confirm command to the nonvolatile memoryapparatus 100, the controller 200 may check whether the pre-command hasbeen transmitted, based on the transmission status. Then, whentransmitting the confirm command, the controller may determine whetherto also transmit the pre-command. When the transmission status of thepre-command is the transmission preparation, the controller 200 maytransmit the confirm command with the pre-command.

When a post-command packet is generated according to the completion ofthe remaining operations while the pre-command is being transmitted tothe nonvolatile memory apparatus 100, between step S107 of transmittingthe pre-command to the nonvolatile memory apparatus 100 and step S111 oftransmitting the confirm command to the nonvolatile memory apparatus100, the controller 200 may wait until the pre-command is completelytransmitted, and then transmit the confirm command to the nonvolatilememory apparatus 100 (see FIG. 7).

FIG. 9 is a diagram illustrating a data processing system 2000 includinga solid state drive (SSD) 2200 in accordance with an embodiment.Referring to FIG. 9, the data processing system 2000 may include a hostdevice 2100 and an SSD 2200.

The SSD 2200 may include a controller 2210, a buffer memory device 2220,nonvolatile memory apparatuses 2231 to 223 n, a power supply 2240, asignal connector 2250 and a power connector 2260.

The controller 2210 may control overall operations of the SSD 2200. Thecontroller 2210 may include an embodiment, such as the controller 200 ofFIG. 2.

The buffer memory device 2220 may temporarily store data to be stored inthe nonvolatile memory apparatuses 2231 to 223 n. The buffer memorydevice 2220 may temporarily store data read from the nonvolatile memoryapparatuses 2231 to 223 n. The data temporarily stored in the buffermemory device 2220 may be transmitted to the host device 2100 or thenonvolatile memory apparatuses 2231 to 223 n under control of thecontroller 2210.

The nonvolatile memory apparatuses 2231 to 223 n may be used as storagemedia of the SSD 2200. The nonvolatile memory apparatuses 2231 to 223 nmay be coupled to the controller 2210 through a plurality of channelsCH1 to CHn, respectively. One channel may be coupled one or morenonvolatile memory apparatuses. The nonvolatile memory apparatusescoupled to one channel may be coupled to the same signal bus and databus.

The power supply 2240 may provide power PWR inputted through the powerconnector 2260 into the SSD 2200. The power supply 2240 may include anauxiliary power supply 2241. The auxiliary power supply 2241 may supplypower to normally shut down the SSD 2200, when a sudden power offoccurs. The auxiliary power supply 2241 may include large capacitorscapable of storing the power PWR.

The controller 2210 may exchange signals SGL with the host device 2100through the signal connector 2250. The signal SGL may include a command,an address, data and the like. The signal connector 2250 may beconfigured as various types of connectors depending on the interfacebetween the host device 2100 and the SSD 2200.

FIG. 10 is a diagram illustrating a configuration of the controller ofFIG. 9. Referring to FIG. 10, the controller 2210 may include a hostinterface unit 2211, a control unit 2212, a RAM 2213, an ECC unit 2214and a memory interface unit 2215.

The host interface unit 2211 may interface the host device 2100 and theSSD 2200 according to a protocol of the host device 2100. For example,the host interface unit 2211 may communicate with the host device 2100through any one of protocols such as SD (Secure Digital), USB (UniversalSerial Bus), MMC (Multi-Media Card), eMMC (Embedded MMC), PCMCIA(Personal Computer Memory Card International Association), PATA(Parallel Advanced Technology Attachment), SATA (Serial AdvancedTechnology Attachment), SCSI (Small Computer System Interface), SAS(Serial Attached SCSI), PCI (Peripheral Component Interconnection),PCI-E (PCI Express) and UFS (Universal Flash Storage). The hostinterface unit 2211 may perform a disk emulation function for supportingthe host device 2100 to recognize the SSD 2200 as a general-purpose datastorage device, for example, an HDD (Hard Disk Drive).

The control unit 2212 may analyze and process a signal received from thehost device 2100. The control unit 2212 may control operations of theinternal function blocks according to firmware or software for operatingthe SSD 2200. The RAM 2213 may be used as a working memory for executingsuch firmware or software.

The ECC unit 2214 may generate parity data of data to be transmitted tothe nonvolatile memory apparatuses 2231 to 223 n. The generated paritydata may be stored in the nonvolatile memory apparatuses 2231 to 223 nwith the data. The ECC unit 2214 may detect errors in data read from thenonvolatile memory apparatuses 2231 to 223 n, based on the parity data.When the detected error falls within a correctable range, the ECC unit2214 may correct the detected error.

The memory interface unit 2215 may provide a control signal such as acommand and address to the nonvolatile memory apparatuses 2231 to 223 nshown in FIG. 9, under control of the control unit 2212. The memoryinterface unit 2215 may exchange data with the nonvolatile memoryapparatuses 2231 to 223 n, under control of the control unit 2212. Forexample, the memory interface unit 2215 may provide data stored in thebuffer memory device 2220 to the nonvolatile memory apparatuses 2231 to223 n, or provide data read from the nonvolatile memory apparatuses 2231to 223 n to the buffer memory device 2220.

FIG. 11 is a diagram illustrating a data processing system including adata storage device in accordance with an embodiment. Referring to FIG.11, the data processing system 3000 may include a host device 3100 and adata storage device 3200.

The host device 3100 may be configured in the form of a board such as aprinted circuit board. Although not illustrated, the host device 3100may include internal function blocks for performing the function of thehost device.

The host device 3100 may include a connection terminal 3110 such as asocket, slot or connector. The data storage device 3200 may be mountedon or in the connection terminal 3110.

The data storage device 3200 may be configured in the form of a boardsuch as a printed circuit board. The data storage device 3200 may bereferred to as a memory module or memory card. The data storage device3200 may include a controller 3210, a buffer memory device 3220,nonvolatile memory apparatuses 3231 and 3232, a PMIC (Power ManagementIntegrated Circuit) 3240 and a connection terminal 3250.

The controller 3210 may control overall operations of the data storagedevice 3200. The controller 3210 may be configured in the same manner asthe controller 2210 illustrated in FIG. 10.

The buffer memory device 3220 may temporarily store data to be stored inthe nonvolatile memory apparatuses 3231 and 3232. The buffer memorydevice 3220 may temporarily store data read from the nonvolatile memoryapparatuses 3231 and 3232. The data temporarily stored in the buffermemory device 3220 may be transmitted to the host device 3100 or thenonvolatile memory apparatuses 3231 and 3232 under control of thecontroller 3210.

The nonvolatile memory apparatuses 3231 and 3232 may be used as storagemedia of the data storage device 3200.

The PMIC 3240 may provide power inputted through the connection terminal3250 into the data storage device 3200. The PMIC 3240 may manage powerof the data storage device 3200 under control of the controller 3210.

The connection terminal 3250 may be connected to the connection terminal3110 of the host device 3100. Through the connection terminal 3250,power and signals such as commands, addresses and data may betransferred between the host device 3100 and the data storage device3200. The connection terminal 3250 may be configured in various mannersdepending on the interface method between the host device 3100 and thedata storage device 3200. The connection terminal 3250 may be disposedon any one side of the data storage device 3200.

FIG. 12 is a diagram illustrating a data processing system including adata storage device in accordance with an embodiment. Referring to FIG.12, the data processing system 4000 may include a host device 4100 and adata storage device 4200.

The host device 4100 may be configured in the form of a board such as aprinted circuit board. Although not illustrated, the host device 4100may include internal function blocks for performing the function of thehost device.

The data storage device 4200 may be configured in the form of a surfacemount package. The data storage device 4200 may be mounted on the hostdevice 4100 through solder balls 4250. The data storage device 4200 mayinclude a controller 4210, a buffer memory device 4220 and a nonvolatilememory apparatus 4230.

The controller 4210 may control overall operations of the data storagedevice 4200. The controller 4210 may be configured in the same manner asthe controller 2210 illustrated in FIG. 10.

The buffer memory device 4220 may temporarily store data to be stored inthe nonvolatile memory apparatus 4230. The buffer memory device 4220 maytemporarily store data read from the nonvolatile memory apparatus 4230.The data temporarily stored in the buffer memory device 4220 may betransmitted to the host device 4100 or the nonvolatile memory apparatus4230 under control of the controller 4210.

The nonvolatile memory apparatus 4230 may be used as a storage medium ofthe data storage device 4200.

FIG. 13 is a diagram illustrating a network system 5000 including a datastorage device in accordance with an embodiment. Referring to FIG. 13,the network system 5000 may include a server system 5300 and a pluralityof client systems 5410 to 5430 which are coupled through a network 5500.

The server system 5300 may service data in response to requests of theplurality of client systems 5410 to 5430. For example, the server system5300 may store data provided from the plurality of client systems 5410to 5430. For another example, the server system 5300 may provide data tothe plurality of client systems 5410 to 5430.

The server system 5300 may include a host device 5100 and a data storagedevice 5200. The data storage device 5200 may be configured as one ormore of the data storage device 10 of FIG. 1, the SSD 2200 of FIG. 9,the data storage device 3200 of FIG. 11, the data storage device 4200 ofFIG. 12, or combinations thereof.

FIG. 14 is a block diagram illustrating a nonvolatile memory apparatusincluded in a data storage device in accordance with an embodiment.Referring to FIG. 14, the nonvolatile memory apparatus 300 may include amemory cell array 310, a row decoder 320, a column decoder 330, a dataread/write block 340, a voltage generator 350 and a control logic 360.

The memory cell array 310 may include memory cells MC arranged at therespective intersections between word lines WL1 to WLm and bit lines BL1to BLn.

The row decoder 320 may be coupled to the memory cell array 310 throughthe word lines WL1 to WLm. The row decoder 320 may operate under controlof the control logic 360. The row decoder 320 may decode an addressprovided from an external device (not illustrated). The row decoder 320may select and drive the word lines WL1 to WLm based on the decodingresult. For example, the row decoder 320 may provide the word lines WL1to WLm with a word line voltage provided from the voltage generator 350.

The data read/write block 340 may be coupled to the memory cell array310 through the bit lines BL1 to BLn. The data read/write block 340 mayinclude read/write circuits RW1 to RWn corresponding to the respectivebit lines BL1 to BLn. The data read/write block 340 may operate undercontrol of the control logic 360. The data read/write block 340 mayoperate as a write driver or a sense amplifier, depending on operationmodes. For example, the data read/write block 340 may operate as a writedriver for storing data, provided from the external device, in thememory cell array 310 during a write operation. For another example, thedata read/write block 340 may operate as a sense amplifier for readingdata from the memory cell array 310 during a read operation.

The column decoder 330 may operate under control of the control logic360. The column decoder 330 may decode an address provided from theexternal device. The column decoder 330 may couple the read/writecircuits RW1 to RWn of the data read/write block 340, corresponding tothe respective bit lines BL1 to BLn, to a data input/output line (ordata input/output buffer), based on the decoding result.

The voltage generator 350 may generate a voltage used for an internaloperation of the nonvolatile memory apparatus 300. The voltagesgenerated by the voltage generator 350 may be applied to the memorycells of the memory cell array 310. For example, a program voltagegenerated during a program operation may be applied to a word line ofmemory cells on which the program operation is to be performed. Foranother example, an erase voltage generated during an erase operationmay be applied to well regions of memory cells on which the eraseoperation is to be performed. For still another example, a read voltagegenerated during a read operation may be applied to a word line ofmemory cells on which the read operation is to be performed.

The control logic 360 may control overall operations of the nonvolatilememory apparatus 300 based on a control signal provided from theexternal device. For example, the control logic 360 may controloperations of the nonvolatile memory apparatus 300, such as read, writeand erase operations of the nonvolatile memory apparatus 300.

While various embodiments have been described above, it will beunderstood to those skilled in the art that the embodiments describedare examples only. Accordingly, the operating process of a data storagedevice described herein should not be limited based on the describedembodiments.

What is claimed is:
 1. A data storage device comprising: a nonvolatilememory apparatus; and a controller configured to: receive a host commandincluding a logical address, determine a physical address correspondingto the logical address, generate a pre-command including the physicaladdress, transmit the generated pre-command to the nonvolatile memoryapparatus before completing performance of one or more remainingoperations used to process the host command, and transmit a confirmcommand to the nonvolatile memory apparatus when performance of theremaining operations is complete, wherein the controller performs theremaining operations and the transmission of the generated pre-commandto the nonvolatile memory apparatus at the same time.
 2. The datastorage device according to claim 1, wherein the controller comprises: amemory configured to store an L2P (Logical-to-Physical) map tableincluding the logical address and the physical address corresponding tothe logical address; a first core configured to translate the logicaladdress into the physical address when the host command is received fromthe host device, transfer a pre-command packet including the translatedphysical address to a second core, and perform the remaining operationsafter transmitting the pre-command packet; and a second core configuredto generate the pre-command according based on the pre-command packetand according to a specification of the host command, transmit thepre-command to the nonvolatile memory apparatus, generate the confirmcommand based on a post-command packet transferred from the first coreafter the performance of the remaining operations is complete, andtransmit the generated confirm command to the nonvolatile memoryapparatus.
 3. The data storage device according to claim 2, wherein thesecond core stores information on a ready or busy status of thenonvolatile memory apparatus, and transmits the pre-command or theconfirm command when the nonvolatile memory apparatus is in the readystatus.
 4. The data storage device according to claim 2, wherein thesecond core manages a transmission status of the pre-command withrespect to the nonvolatile memory apparatus, the transmission statusbeing any one of transmission start, transmission finish, andtransmission preparation, and wherein the second core checks whether thepre-command has been transmitted, based on the transmission status,before transmitting the confirm command to the nonvolatile memoryapparatus, and determines whether to transmit the pre-command whentransmitting the confirm command.
 5. The data storage device accordingto claim 2, wherein in response to the controller receiving a host abortcommand before the post-command packet has been transmitted to thesecond core, the first core aborts a procedure of transmitting thepost-command packet to the second core.
 6. The data storage deviceaccording to claim 2, wherein in response to the controller receiving ahost abort command before the post-command packet has been transmittedto the second core, the first core transmits a post-command packetincluding an abort request to the second core, wherein in response toreceiving the post-command packet including the abort request, thesecond core aborts transmitting the pre-command to the nonvolatilememory apparatus.
 7. The data storage device according to claim 2,wherein when in response to the second core receiving the post-commandpacket from the first core while the second core is transmitting thepre-command to the nonvolatile memory apparatus, the second core waitsuntil the pre-command is completely transmitted, and then transmits theconfirm command to the nonvolatile memory apparatus.
 8. The data storagedevice according to claim 1, wherein when the host command is a readcommand, the controller generates the pre-command packet including adata storage method, a flash read command indication, and addressinformation.
 9. The data storage device according to claim 1, whereinwhen the host command is a write command, the controller generates thepre-command packet including a data storage method, flash write commandindication, address information, and data to be written, or generatesthe pre-command packet including a data storage method, the flash writecommand indication, and address information.
 10. An operating method ofa data storage device, the method comprising: receiving a host commandincluding a logical address; determining a physical addresscorresponding to the logical address; generating, according to aspecification of the host command, a pre-command which includes thephysical address; transmitting the pre-command to the nonvolatile memoryapparatus before completing one or more remaining operations used toprocess the host command; performing the remaining operations; andtransmitting a confirm command to the nonvolatile memory apparatus whenperforming the remaining operations is complete, wherein performance ofthe remaining operations and transmission of the pre-command to thenonvolatile memory apparatus occur at a same time.
 11. The operatingmethod according to claim 10, wherein when the nonvolatile memoryapparatus is in a ready status, the pre-command or the confirm commandis transmitted to the nonvolatile memory apparatus.
 12. The operatingmethod according to claim 10, further comprising managing a transmissionstatus of the pre-command with respect to the nonvolatile memoryapparatus, the transmission status being any one of transmission start,transmission finish, and transmission preparation.
 13. The operatingmethod according to claim 10, further comprising: generating apost-command packet in response to completion of the remainingoperations; generating the confirm command according to the post-commandpacket; and when transmission of the pre-command has not completed andthe post-command packet has been generated: waiting for transmission ofthe pre-command to complete, and transmitting the confirm command to thenonvolatile memory apparatus in response to the completion of thetransmission of the pre-command.
 14. The operating method according toclaim 10, wherein when the host command is a read command, generatingthe pre-command packet comprises generating the pre-command packetincluding a data storage method, a flash read command indication, andaddress information.
 15. The operating method according to claim 10,wherein when the host command is a write command, generating thepre-command packet comprises: generating the pre-command packetincluding a data storage method, a flash write command indication,address information, and data to be written; or generating thepre-command packet including a data storage method, the flash writecommand indication, and address information.
 16. The operating methodaccording to claim 10, wherein when the host command is a read command,determining the physical address corresponding to the logical addresscomprises translating the logical address into the physical address byreferring to a previously-stored Logical-to-Physical (L2P) map table.17. The operating method according to claim 10, wherein when the hostcommand is a write command, determining the physical addresscorresponding to the logical address comprises setting a physicaladdress to which data corresponding to the logical address is to bewritten.